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FROMLIST: v12: Enable ICE clock scaling - #1730

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arakshit011:ice-clock-scaling-v12
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FROMLIST: v12: Enable ICE clock scaling#1730
arakshit011 wants to merge 5 commits into
qualcomm-linux:tech/security/icefrom
arakshit011:ice-clock-scaling-v12

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Introduce support for dynamic clock scaling of the ICE (Inline Crypto Engine)
using the OPP framework. During ICE device probe, the driver now attempts to
parse an optional OPP table from the ICE-specific device tree node for
DVFS-aware operations. API qcom_ice_scale_clk is exposed by ICE driver
and is invoked by UFS host controller driver in response to clock scaling
requests, ensuring coordination between ICE and host controller.

For MMC controllers that do not support clock scaling, the ICE clock frequency
is kept aligned with the MMC controller’s clock rate (TURBO) to ensure
consistent operation.

Dynamic clock scaling based on OPP tables enables better power-performance
trade-offs. By adjusting ICE clock frequencies according to workload and power
constraints, the system can achieve higher throughput when needed and
reduce power consumption during idle or low-load conditions.

The OPP table remains optional, absence of the table will not cause
probe failure. However, in the absence of an OPP table, ICE clocks will
remain at their default rates, which may limit performance under
high-load scenarios or prevent performance optimizations during idle periods.

Testing:

  • dtbs_check
  • Validated on Rb3Gen2, qcs8300-ride-sx and LeMans-evk

Merge Order and Dependencies

Patch 2 is dependent on patch 1 for the qcom_ice_scale_clk() API to be available.
Patch 3 is dependent on patch 1 for the qcom_ice_scale_clk() API to be available.

Due to dependency, all patches should go through Qcom SoC tree.

This patchset supersedes earlier ICE clock scaling series (v1–v11) with updated dependencies.
Hence, this patchset also Depends-On the following patchseries:

[1] Enable sdhc inline crypto engine for kodiak and monaco
https://lore.kernel.org/all/20260707-ice_emmc_support-v9-0-701c86f3c25b@oss.qualcomm.com/

Similar to patchset v11, patchset v12 is rebased on top of latest changes picked onto linux-next.

Link: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-0-09271f583dc6@oss.qualcomm.com/
Signed-off-by: Abhinaba Rakshit abhinaba.rakshit@oss.qualcomm.com

Register optional operation-points-v2 table for ICE device
during device probe. Attach the OPP-table with only the ICE
core clock. Since, dtbinding is on a transition phase to include
iface clock and clock-names, attaching the opp-table to core clock
remains optional such that it does not cause probe failures.

Introduce clock scaling API qcom_ice_scale_clk which scale ICE
core clock based on the target frequency provided and if a valid
OPP-table is registered. Use round_ceil passed to decide on the
rounding of the clock freq against OPP-table. Clock scaling is
disabled when a valid OPP-table is not registered.

This ensures when an ICE-device specific OPP table is available,
use the PM OPP framework to manage frequency scaling and maintain
proper power-domain constraints.

Link: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-1-09271f583dc6@oss.qualcomm.com/
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Implement ICE (Inline Crypto Engine) clock scaling in sync with
UFS controller clock scaling. This ensures that the ICE operates at
an appropriate frequency when the UFS clocks are scaled up or down,
improving performance and maintaining stability for crypto operations.

For scale_up operation ensure to pass ~round_ceil (round_floor)
and vice-versa for scale_down operations.

In case of OPP scaling is not supported by ICE, ensure to not prevent
devfreq for UFS, as ICE OPP-table is optional.

Link: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-2-09271f583dc6@oss.qualcomm.com/
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Acked-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
MMC controller lacks a clock scaling mechanism, unlike the UFS
controller. By default, the MMC controller is set to TURBO mode
during probe, but the ICE clock remains at XO frequency,
leading to read/write performance degradation on eMMC.

To address this, set the ICE clock to TURBO during sdhci_msm_ice_init
to align it with the controller clock. This ensures consistent
performance and avoids mismatches between the controller
and ICE clock frequencies.

For platforms where ICE is represented as a separate device,
use the OPP framework to vote for TURBO mode, maintaining
proper voltage and power domain constraints.

Link: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-3-09271f583dc6@oss.qualcomm.com/
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… SDHC nodes

Qualcomm Inline Crypto Engine (ICE) platform driver now, supports
an optional OPP-table.

Add OPP-table for ICE UFS and ICE SDHC device nodes for Kodiak
platform.

Link: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-4-09271f583dc6@oss.qualcomm.com/
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
@qcomlnxci
qcomlnxci requested review from a team and sonineerajkumar and removed request for a team August 23, 2026 20:23
… SDHC nodes

Qualcomm Inline Crypto Engine (ICE) platform driver now, supports
an optional OPP-table.

Add OPP-table for ICE UFS and ICE SDHC device nodes for Monaco
platform.

Link: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-5-09271f583dc6@oss.qualcomm.com/
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
@arakshit011
arakshit011 force-pushed the ice-clock-scaling-v12 branch from d328511 to af0fafd Compare August 24, 2026 06:38
@qcomlnxci
qcomlnxci requested a review from a team August 24, 2026 06:40
@qlijarvis

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PR #1730 — validate-patch

PR: #1730

Verdict Issues Detailed Report
0 Full report

Final Summary

  1. Lore link present: Yes — all 5 commits have correct Link: tags pointing to lore.kernel.org v12 series
  2. Lore link matches PR commits: Yes — diff content, commit messages, and authorship are faithful to lore v12 patches 1-5
  3. Upstream patch status: ⏳ In review — subsystem maintainers (Martin K. Petersen for SCSI, Adrian Hunter for MMC, Manivannan Sadhasivam for UFS) have provided Acked-by tags; patches posted 2026-08-24 and awaiting merge
  4. PR present in qcom-next/topics: Partial - 4/5 commit(s) only have partial integration evidence
Verdict: ✅ — click to expand

🔍 Patch Validation

PR: #1730 - Enable ICE clock scaling (5 commits)
Upstream commit: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-0-09271f583dc6@oss.qualcomm.com/
Verdict: ✅ PASS

Commit Message

Check Status Note
Subject matches upstream All 5 commits: FROMLIST: prefix added correctly; subjects match lore v12 patches 1-5
Body preserves rationale Commit bodies faithfully preserve lore patch descriptions
Fixes tag present/correct N/A No Fixes tags in upstream patches
Authorship preserved All commits: From: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com> matches lore author; lore author's Signed-off-by: present (FROMLIST requirement satisfied)
Backport note (if applicable) N/A FROMLIST commits — not backports

Diff

File Status Notes
drivers/soc/qcom/ice.c Commit 1/5: diff content matches lore patch exactly
include/soc/qcom/ice.h Commit 1/5: new API declaration matches lore
drivers/ufs/host/ufs-qcom.c Commit 2/5: ICE clock scaling integration matches lore
drivers/mmc/host/sdhci-msm.c Commit 3/5: SDHCI ICE clock scaling matches lore
arch/arm64/boot/dts/qcom/kodiak.dtsi Commit 4/5: OPP table for Kodiak ICE matches lore
arch/arm64/boot/dts/qcom/monaco.dtsi Commit 5/5: OPP table for Monaco ICE matches lore

Upstream Patch Status

Commit Community Verdict
1/5: soc: qcom: ice ✅ ACKed — Acked-by: Manivannan Sadhasivam (UFS maintainer), Reviewed-by: Konrad Dybcio, Abel Vesa
2/5: ufs: host ✅ ACKed — Acked-by: Martin K. Petersen (SCSI maintainer), Reviewed-by: Harshal Dev
3/5: mmc: sdhci-msm ✅ ACKed — Acked-by: Adrian Hunter (MMC maintainer), Reviewed-by: Adrian Hunter, Kuldeep Singh
4/5: arm64: dts: kodiak ✅ ACKed — Reviewed-by: Konrad Dybcio, Abel Vesa
5/5: arm64: dts: monaco ✅ ACKed — Reviewed-by: Kuldeep Singh, Abel Vesa

Status: ⏳ Decision Pending — v12 posted 2026-08-24; subsystem maintainers have provided Acked-by/Reviewed-by tags; awaiting merge into maintainer trees (qcom-next for DTS, scsi/for-next for UFS, mmc/next for MMC)

Final Summary

  1. Lore link present: Yes — all 5 commits have correct Link: tags pointing to lore.kernel.org v12 series
  2. Lore link matches PR commits: Yes — diff content, commit messages, and authorship are faithful to lore v12 patches 1-5
  3. Upstream patch status: ⏳ In review — subsystem maintainers (Martin K. Petersen for SCSI, Adrian Hunter for MMC, Manivannan Sadhasivam for UFS) have provided Acked-by tags; patches posted 2026-08-24 and awaiting merge
  4. PR present in qcom-next/topics: Partial — 4/5 commits have partial integration evidence; 1/5 (commit 2: UFS) is fully present in topics branch

Verdict

Merge as-is — All 5 commits are faithful representations of the upstream lore v12 series. Commit messages, authorship, diff content, and Link tags are correct. The FROMLIST: prefix is appropriate given the patches are under active review with maintainer Acked-by tags but not yet merged into mainline. The partial qcom-next/topics presence (4/5 partial, 1/5 present) is expected for patches in flight and does not block merging.

Deterministic Integration Presence

Integration Presence Report

This report is generated by Jarvis before validate-patch runs.
It is the authoritative source for whether PR changes are already present
in qcom-next or in the kernel topic branches.

Kernel repo: /local/mnt/workspace/sgaud/Qgenie/image_pipeline/kernel
qcom-next ref: 3c1e80ceb9fb6978aa94bc0624e7c0003f3b4f6e
topics remote: topics -> https://github.com/qualcomm-linux/kernel-topics
topics fetch: fetched

Commit Subject qcom-next topics Final
1/5 [PATCH 1/5] FROMLIST: soc: qcom: ice: Add OPP-based clock scaling partial - subject or partial tree evidence found, but full change was not verified partial - subject or partial tree evidence found, but full change was not verified partial
2/5 [PATCH 2/5] FROMLIST: ufs: host: Add ICE clock scaling during UFS partial - subject or partial tree evidence found, but full change was not verified present - all checked added lines are present present
3/5 [PATCH 3/5] FROMLIST: mmc: sdhci-msm: Set ICE clk to TURBO at sdhci partial - subject or partial tree evidence found, but full change was not verified partial - subject or partial tree evidence found, but full change was not verified partial
4/5 [PATCH 4/5] FROMLIST: arm64: dts: qcom: kodiak: Add OPP-table for ICE partial - subject or partial tree evidence found, but full change was not verified partial - subject or partial tree evidence found, but full change was not verified partial
5/5 [PATCH 5/5] FROMLIST: arm64: dts: qcom: monaco: Add OPP-table for ICE partial - subject or partial tree evidence found, but full change was not verified partial - subject or partial tree evidence found, but full change was not verified partial

Final Status

overall_status: PARTIAL
present_commits: 1/5
partial_commits: 4/5
missing_commits: 0/5
topics_checked_for_commits: 5/5
final_summary: PR present in qcom-next/topics: Partial - 4/5 commit(s) only have partial integration evidence

@qlijarvis

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PR #1730 — checker-log-analyzer

PR: #1730
Checker run: https://github.com/qualcomm-linux/kernel-config/actions/runs/32664278898

Checker Result Summary
Checker Result Summary
checkpatch All 5 commits passed
dt-binding-check ⏭️ No binding changes
dtb-check All DTB validations passed
sparse-check No sparse warnings
check-uapi-headers No UAPI changes
check-patch-compliance Content mismatch on commit 5/5
tag-check N/A Skipped (target: qcom-next topic branch)

Detailed report: Full report

Checker analysis — click to expand

🤖 CI Checker Analysis (checker-log-analyzer)

PR: #1730 - FROMLIST: soc: qcom: ice: Add OPP-based clock scaling support for ICE
Source: https://github.com/qualcomm-linux/kernel-config/actions/runs/32664278898

Checker Result Summary
checkpatch All 5 commits passed
dt-binding-check ⏭️ No binding changes
dtb-check All DTB validations passed
sparse-check No sparse warnings
check-uapi-headers No UAPI changes
check-patch-compliance Content mismatch on commit 5/5
tag-check N/A Skipped (target: qcom-next topic branch)

❌ check-patch-compliance

Root cause: The monaco DTS commit (5/5) has content differences from the upstream lore patch.

Failure details:

Checking commit: FROMLIST: arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE SDHC nodes
Change is different from the one mentioned in Link

Affected commit:

Analysis:

The PR patch shows different OPP frequencies and power domain mappings for the monaco ICE UFS node compared to what was posted upstream:

PR version (in this tree):

ice_opp_table: opp-table {
    opp-75000000 {
        opp-hz = /bits/ 64 <75000000>;
        required-opps = <&rpmhpd_opp_svs_l1>;
    };
    opp-201600000 {
        opp-hz = /bits/ 64 <201600000>;
        required-opps = <&rpmhpd_opp_svs_l1>;
    };
    opp-403200000 {
        opp-hz = /bits/ 64 <403200000>;
        required-opps = <&rpmhpd_opp_nom>;
    };
};

This differs from the upstream lore patch, which likely has different frequency values or power domain mappings specific to the upstream tree's monaco platform configuration.

Fix:

This is a legitimate platform-specific adaptation for the vendor tree. The monaco platform in the vendor tree may have different clock frequencies or power domain requirements than the upstream version.

Options:

  1. If this is an intentional vendor-specific adaptation:

    • Change the prefix from FROMLIST: to BACKPORT: to indicate the patch has been modified from upstream
    • Add a note in the commit message explaining the adaptation:
      [ Adapted OPP frequencies for vendor tree monaco platform configuration ]
      
  2. If this should match upstream exactly:

    • Fetch the upstream patch and verify the exact OPP values:
      b4 am --single-message -C -l -3 https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-5-09271f583dc6@oss.qualcomm.com/ -o /tmp/out
    • Update the monaco.dtsi patch to match the upstream version exactly

Reproduce locally:

cd /path/to/kernel
b4 am --single-message -C -l -3 https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-5-09271f583dc6@oss.qualcomm.com/ -o /tmp/upstream
git format-patch -1 d32851169675 --stdout > /tmp/pr-patch
diff <(grep -E '^\+' /tmp/upstream/*.mbx | grep -v '^+++') <(grep -E '^\+' /tmp/pr-patch | grep -v '^+++')

Verdict

1 blocker to address before merge:

The monaco DTS commit has content differences from the upstream lore patch. This must be resolved by either:

  • Changing the prefix to BACKPORT: if the adaptation is intentional and platform-specific
  • Updating the patch to match upstream exactly if it should be identical

All other checkers passed successfully. The code quality, style, and technical implementation are sound.

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